JP-A 2011-129566 (Patent Literature 1) discloses a structure of dynamic random access memory (DRAM) cells having field effect transistors as selection transistors each having a buried gate electrode structure.
In this technology, a bottom portion of each of grooves formed in a silicon substrate (semiconductor substrate) is filled with a conductive film while an insulation film is interposed between the conductive film and inner surfaces of the groove. In this manner, a metal insulator semiconductor (MIS) structure is formed at the bottom portion of each of the grooves. Source/drain (S/D) regions are drawn from an upper surface of the silicon substrate.
One of the S/D regions is connected to a bit line, and the other S/D region is connected to a capacitor. Thus, a DRAM cell is formed.
Meanwhile, in a buried gate type MIS transistor disclosed in Patent Literature 1, a gate electrode (buried gate electrode) is arranged at the bottom of a groove formed in an active region while a gate insulation film is interposed between the gate electrode and inner surfaces of the groove.
Therefore, when an ON-state voltage is applied to a buried gate electrode, an inversion layer (channel) is formed at a deep location from the same level as an upper surface of the buried gate electrode as seen in the depth direction of the silicon substrate.
Specifically, when a buried gate type MIS transistor is turned on, carriers drift in a semiconductor region from an S/D contact portion on a surface of a silicon substrate (a contact portion between a contact plug and an S/D region) to an upper surface of the buried gate electrode in which a channel is formed.
Therefore, the depth of the gate electrode being buried affects the device characteristics. In this regard, there is a room for improving a structure of a buried gate type MIS transistor.